1. Field of the Invention
The present invention relates to image or video processing systems and more particularly to automatic color control and chroma killer (ACC/ACK) circuit.
2. Background of the Invention
In the prior art, there have been various image or video processing systems. An example is a digital television receiver in which a video signal of base band is digitized by an A/D converter, processed digitally and finally displayed as an analog signal by means of a D/A converter. Such devices feature relative ease of regulation and improvement of image quality by applying precision delay elements and various signal processing systems.
A prior art block circuit diagram of an image or video processing system, such as a television is depicted in FIG. 16, with reference to which signal processing will be described briefly. In FIG. 16, an input terminal for receiving an analog composite signal of base band is branched to signal and synchronizing processing systems, said signal processing system comprises an A/D converter 1, a Y (luminance signal)/ C (chrominance signal) separator 2, a digital automatic color control (ACC) circuit 3, a color demodulator 10, a matrix circuit 4, and a D/A converter 5. Said synchronizing processing system comprises a burst gate 6, a synchronizing signal separator 7, a clock generator 8 and a synchronizing signal processor 9.
In the image or video processing system, the analog composite video signal input to the A/D converter 1 is converted into a digital signal and the luminance and chrominance signals thereof are separated by the Y/C separator 2. The chrominance signal is input to the demodulator 10 through the ACC circuit 3. The demodulator 10 generates a R-Y signal and a B-Y signal and supplies them to the matrix circuit 4. The matrix circuit 4 generates R, G and B signals by processing the R-Y and B-Y signals and supplies them to the D/A converter 5. The D/A converter 5 converts them back into analog R, G and B signals and supplies them to a video display device such as a monitor, etc.
Simultaneously, in the synchronizing processing system, a burst signal which is used as a reference of color phase is derived by the burst gate 6 from said analog composite video signal and a composite synchronizing signal is derived by the synchronizing signal separator 7 from the composite video signal. The composite synchronizing signal is processed in the synchronizing signal processor 9 and a horizontal synchronizing signal is supplied to the ACC circuit 3. The burst signal is supplied to the clock generator 8. The clock generator 8 generates a clock (4 fsc clock) having frequency four times that of the burst signal and supplies them to various portions of the signal processing system. Signals input to the various portions of the signal processing system are sampled at the 4 fsc clock rate.
One of the problems in a video or image processing system is that broadcast amplitudes of color signals change since the level of a composite video signal depends upon the respective TV channel. In those cases, amplitude variation may be reproduced as a variation of color saturation when R, G and B signals are generated by the matrix circuit 4. This necessitates implementation of ACC circuit 3 to maintain constant amplitude by modifying incoming color signals according to variations detected apart from a norm. Since the amplitude of the burst signal is determined according to a standard, it is possible to calculate gain necessary for a color signal within a horizontal line period in which the burst signal exists by checking an amplitude variation value of the burst signal and adjusting signal amplitude with the ACC 3.
However, there is another problem in receiving broadcast waves; there are signals containing no burst signal or signals whose S/N ratio or higher frequency gain are degraded significantly. These signals may coexist with signals containing burst signals. In such cases, a detected burst signal value becomes unstable and, if processed by the ACC circuit 3 without modification, a chroma component may be amplified in the color signal. Therefore, if the burst signal is smaller in amplitude than the constant amplitude detection value, reproduction of the color signal must be prevented automatically. This can be done with a chroma killer circuit. Additionally, the function of automatic color controlling and chroma killing has been realized in prior art by combining an ACC circuit and a chroma killer circuit.
A block circuit diagram of a prior art digital ACC circuit having a killer circuit is shown in FIG. 15. This conventional digital ACC circuit 3 is comprised of a multiplier 11, an amplitude detector 12, a horizontal average circuit 13, a divider 14, a vertical filter 15 and a killer circuit including a comparator 16 and a selector 17.
The multiplier 11 is supplied with color signals obtained by the Y/C separation of the composite video signals. The amplitude detector 12 performs an arithmetic operation (two squaring calculations) for obtaining an absolute value of the amplitude of the burst signal. Then, the horizontal average circuit 13 develops a horizontal average from the output signal of the amplitude detector 12. The divider 14 divides the horizontal average value by a reference value (reference data). The vertical filter 15 accumulates an output value from the divider 14 for ten or more lines, averages them, and supplies the averaged value to the multiplier 11 where it is multiplied with the input color signal. Thus, it is possible to make the amplitude of the color signal constant. In this case, the accumulation and averaging by means of the vertical filter 15 is to accommodate an abrupt change of multiplier due to erroneous detection of noise, etc. Since with respect to an input signal, there are few factors causing the burst signal to be changed abruptly, a time constant of the vertical filter 15 is made large.
In the killer circuit defined by a dotted line, the comparator 16 compares a multiplier determined through the vertical filter 15 with a preliminarily set maximum multiplier to identify whether the multiplier obtained from the vertical filter 15 has an unintentionally large value and, when it is larger than the maximum multiplier, provides a multiplier "0" to the multiplier 11 by switching the selector 17. As a result, the multiplier circuit 11 outputs a color signal "0" performing a chroma killer operation.
The problem with the prior art digital ACC and killer circuit is that in order to perform arithmetic operations with such construction, large scale hardware is necessary. More particularly, large scale hardware is required for implementation of the divider 14 and vertical filter 15. In addition, simplification of algorithms capable of performing digital ACC functions without degrading performance is desired. To satisfy part of the problem of reducing structure, a digital ACC circuit was developed and disclosed in Japanese Patent Application No. H3-211630. However, development of a compatible and reduced structure chroma killer circuit continued to be sought.